The present disclosure relates to a method for fabricating a metal interconnection of a semiconductor device. As semiconductor device fabrication technology develops, semiconductor devices have become smaller and more highly integrated. While semiconductor devices are fabricated according to 130-nm and 90-nm design rules, semiconductor device fabrication technology meeting 65-nm or 45-nm design rules have been developed.
Due to the higher integration of semiconductor devices, interconnections have been made smaller. Increasing interest has focused on copper interconnections. Copper interconnections have lower resistance and higher electro-migration than aluminum or aluminum alloy interconnections. Copper interconnections may be fabricated using a “Damascene process.”
A damascene process is a process that forms a trench and a via hole exposing a lower interconnection in an insulation layer, deposits a copper layer within the trench and the via hole, and planarizes the copper layer through a chemical mechanical polishing (CMP) process to form a copper interconnection. In particular, since an etch stop layer on the lower interconnection is formed of nitride, the lower interconnection must be exposed by selectively removing the etch stop layer after forming the via hole and the trench.
However, due to the small size of the interconnections, a critical dimension (CD) of the via hole gets smaller. Polymer remains inside the via hole as an etch by-product generated inside during the formation of the via hole, which causes defects. If an excessive chemical process is performed to remove the polymer residue inside the via hole, a sidewall of the via hole becomes rough, and the hole becomes narrow.
In addition, a barrier metal may be deposited before the insides of the trench and the via hole are filled with a copper layer. Since the polymer residue makes it difficult to remove the etch stop layer, the barrier metal may not be uniformly deposited, which will lower the yield of products.
Those limitations are caused because it is difficult to completely remove the polymer residue generated as a process by-product. Meanwhile, void issues may be caused by a by-product generated by secondary contamination in a wet etching process.